Socket | AMD Socket G34 | Intel Socket 1200 |
---|---|---|
Taille du processus | 32 nm | 14 nm |
Transistors | 2,400 million | unknown |
Taille des matrices | 315 mm² | unknown |
Package | — | FC-LGA1200 |
Fonderie | — | Intel |
tCaseMax | — | 72°C |
tJMax | — | 100°C |
Fréquence | 2.8 GHz | 2.8 GHz |
---|---|---|
Turbo clock | up to 3.5 GHz | up to 4.5 GHz |
Base clock | 200 MHz | 100 MHz |
Multiplicateur | 14.0x | 28.0x |
Multiplicateur débloqué | No | Yes |
TDP | 140 W | 65 W |
Marché | Server/Workstation | Server/Workstation |
---|---|---|
État de la production | unknown | Active |
Date de sortie | Nov 5th, 2012 | Sep 8th, 2021 |
Nom de code | Abu Dhabi | Rocket Lake-E |
Génération | Opteron | Xeon |
Part | OS6386YETGGHK | unknown |
Support mémoire | DDR3 | DDR4-3200 MHz Dual-channel |
La mémoire du CEC | No | Yes |
PCI Express | Gen 2 | Gen 4, 44 Lanes(CPU only) |
Nombre de cœurs | 16 | 4 |
---|---|---|
Nombre de threads | 16 | 4 |
SMP # CPUs | 4 | 1 |
Cartes graphiques intégrées | — | — |
Cache L1 | 768K | 64K (per core) |
---|---|---|
Cache L2 | 16MB | 512K (per core) |
Cache L3 | 8MB (per die) | 8MB (shared) |
Remarques | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). | — |
---|
ABM | — | Yes |
---|---|---|
ADX | — | Yes |
AES | Yes | — |
AES-NI | — | Yes |
AMD-V | Yes | — |
AMD64 | Yes | — |
AVX | Yes | Yes |
AVX 1.1 | Yes | — |
AVX2 | — | Yes |
AVX512 | — | Yes |
BMI1 | — | Yes |
BMI2 | — | Yes |
CLMUL | Yes | Yes |
CVT16 | Yes | — |
EIST | — | Yes |
F16C | Yes | Yes |
FMA3 | Yes | Yes |
FMA4 | Yes | — |
Intel 64 | — | Yes |
MMX | Yes | Yes |
RdRand | — | Yes |
SHA | — | Yes |
SSE | Yes | Yes |
SSE2 | Yes | Yes |
SSE3 | Yes | Yes |
SSE4.1 | Yes | — |
SSE4.2 | Yes | Yes |
SSE4A | Yes | — |
SSSE3 | Yes | Yes |
TBT 2.0 | — | Yes |
TSX | — | Yes |
TXT | — | Yes |
VT-d | — | Yes |
VT-x | — | Yes |
XD bit | — | Yes |
XOP | Yes | — |