Socket | AMD Socket AM3+ | Intel Socket 1155 |
---|---|---|
Taille du processus | 32 nm | 22 nm |
Transistors | 1,200 million | 1,400 million |
Taille des matrices | 315 mm² | 160 mm² |
Package | µPGA | FC-LGA12C |
Fonderie | — | Intel |
Fréquence | 3.2 GHz | 3.3 GHz |
---|---|---|
Turbo clock | up to 4 GHz | up to 3.7 GHz |
Base clock | 200 MHz | 100 MHz |
Multiplicateur | 16.0x | 33.0x |
Multiplicateur débloqué | Yes | No |
Tension | 1.425 V | — |
TDP | 95 W | 69 W |
Marché | Desktop | Server/Workstation |
---|---|---|
État de la production | Active | unknown |
Date de sortie | Sep 2nd, 2014 | May 14th, 2012 |
Nom de code | Vishera | Ivy Bridge |
Génération | FX | Xeon E3 |
Part | FD832EWMW8KHKFD832EWMHKBOX | SR0P4 |
Support mémoire | DDR3 Dual-channel | DDR3 Dual-channel |
La mémoire du CEC | No | Yes |
PCI Express | Gen 2 | Gen 3, 16 Lanes(CPU only) |
Nombre de cœurs | 8 | 4 |
---|---|---|
Nombre de threads | 8 | 8 |
SMP # CPUs | 1 | 1 |
Cartes graphiques intégrées | — | — |
Cache L1 | 384K | 64K (per core) |
---|---|---|
Cache L2 | 8MB | 256K (per core) |
Cache L3 | 8MB (shared) | 8MB (shared) |
Remarques | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). This processor comes with an unlocked multiplier, allowing users to set the multiplier value higher than the shipped | — |
---|
AES | Yes | — |
---|---|---|
AES-NI | — | Yes |
AMD-V | Yes | — |
AMD64 | Yes | — |
AVX | Yes | Yes |
CLMUL | Yes | — |
CVT16 | Yes | — |
ECC | — | Yes |
EIST | — | Yes |
EVP | Yes | — |
FMA4 | Yes | — |
HT3.1 | Yes | — |
HTT | — | Yes |
Intel 64 | — | Yes |
MMX | Yes | Yes |
SSE | Yes | Yes |
SSE2 | Yes | Yes |
SSE3 | Yes | Yes |
SSE4.1 | Yes | — |
SSE4.2 | Yes | Yes |
SSE4A | Yes | — |
SSSE3 | Yes | Yes |
TXT | — | Yes |
Turbo Core | Yes | — |
VT-d | — | Yes |
VT-x | — | Yes |
XD bit | — | Yes |
XOP | Yes | — |