AMD A6-9550 vs AMD A8-4500M
Physical Specifications
Socket | AMD Socket AM4 | AMD Socket FS1r2 |
---|---|---|
Process size | 28 nm | 32 nm |
Transistors | 1,178 million | 1,178 million |
Die size | 246 mm² | 246 mm² |
Package | µPGA | µPGA |
tCaseMax | 74°C | — |
Performance
Frequency | 3.8 GHz | 1900 MHz |
---|---|---|
Turbo clock | up to 4 GHz | up to 2.8 GHz |
Base clock | 100 MHz | 100 MHz |
Multiplier | 38.0x | 19.0x |
Multiplier unlocked | Yes | No |
Voltage | 1.475 V | 1.3 V |
TDP | 65 W | 35 W |
Architecture Details
Vertical Segment | Desktop | Mobile |
---|---|---|
Production status | Active | unknown |
Release date | Jul 27th, 2017 | May 15th, 2012 |
Codename | Bristol Ridge | Trinity |
Generation | A6 | A8 |
Part | AD9550AGM23AB | AM4500DEC44HJ |
Memory support | DDR4 Dual-channel | unknown |
ECC memory | No | No |
Cores
Total Cores | 2 | 4 |
---|---|---|
Total Threads | 2 | 4 |
SMP # CPUs | 1 | 1 |
Integrated graphics | Radeon R5 | Radeon HD 7640G |
Cache
Cache L1 | 128K (per core) | 192K |
---|---|---|
Cache L2 | 1MB (per core) | 4MB (shared) |
Notes
Notes | This processor comes with an unlocked base clock multiplier, allowing users to set the multiplier value higher than shipped value, to facilitate better overclocking. | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). 497MHz integrated graphics base core frequency, 655MHz maximum dynamic core frequency |
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Features & Technologies
3DNow! | Yes | — |
---|---|---|
AES | Yes | Yes |
AMD-V | Yes | Yes |
AMD64 | Yes | Yes |
AVX | Yes | Yes |
AVX2 | Yes | — |
BMI1 | Yes | — |
BMI2 | Yes | — |
CLMUL | — | Yes |
CVT16 | — | Yes |
EVP | Yes | Yes |
F16C | Yes | Yes |
FMA3 | Yes | Yes |
FMA4 | Yes | Yes |
MMX | Yes | Yes |
SSE | Yes | Yes |
SSE2 | Yes | Yes |
SSE3 | Yes | Yes |
SSE4 | Yes | — |
SSE4.1 | Yes | Yes |
SSE4.2 | Yes | Yes |
SSE4A | Yes | Yes |
SSSE3 | — | Yes |
TBM | Yes | — |
Turbo Core | Yes | Yes |
XOP | Yes | Yes |