Socket | AMD Socket G34 | Intel Socket 1155 |
---|---|---|
Taille du processus | 32 nm | 32 nm |
Transistors | 2,400 million | 1,160 million |
Taille des matrices | 316 mm² | 216 mm² |
Package | — | FC-LGA10 |
Fonderie | — | Intel |
Fréquence | 2.6 GHz | 3.4 GHz |
---|---|---|
Turbo clock | up to 3.3 GHz | up to 3.8 GHz |
Base clock | 200 MHz | 100 MHz |
Multiplicateur | 13.0x | 34.0x |
Multiplicateur débloqué | No | No |
TDP | 140 W | 95 W |
Marché | Server/Workstation | Server/Workstation |
---|---|---|
État de la production | End-of-life | End-of-life |
Date de sortie | Nov 14th, 2011 | Apr 3rd, 2011 |
Nom de code | Interlagos | Sandy Bridge |
Génération | Opteron | Xeon E3 |
Part | OS6282YETGGGU | SR00P |
Support mémoire | DDR3 | DDR3 Dual-channel |
La mémoire du CEC | No | Yes |
PCI Express | Gen 2 | Gen 3, 16 Lanes(CPU only) |
Nombre de cœurs | 16 | 4 |
---|---|---|
Nombre de threads | 16 | 8 |
SMP # CPUs | 4 | 1 |
Cartes graphiques intégrées | — | Intel HD P3000 |
Cache L1 | 768K | 64K (per core) |
---|---|---|
Cache L2 | 16MB | 256K (per core) |
Cache L3 | 8MB (per die) | 8MB (shared) |
Remarques | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). 8MB L3 cache shared per eight cores (per die). 14MB total L3 cache available when using HT Assist. | — |
---|
AES | Yes | — |
---|---|---|
AES-NI | — | Yes |
AMD-V | Yes | — |
AMD64 | Yes | — |
AVX | Yes | Yes |
CLMUL | Yes | — |
CVT16 | Yes | — |
EIST | — | Yes |
EVP | Yes | — |
FMA4 | Yes | — |
HTT | — | Yes |
Intel 64 | — | Yes |
MMX | Yes | Yes |
SSE | Yes | Yes |
SSE2 | Yes | Yes |
SSE3 | Yes | Yes |
SSE4.1 | Yes | — |
SSE4.2 | Yes | Yes |
SSE4A | Yes | — |
SSSE3 | Yes | Yes |
TXT | — | Yes |
VT-d | — | Yes |
VT-x | — | Yes |
XD bit | — | Yes |
XOP | Yes | — |