Socket | AMD Socket G34 | Intel Socket 2011 |
---|---|---|
Tamaño del proceso | 32 nm | 32 nm |
Transistores | 2,400 million | 2,270 million |
Tamaño de Die | 316 mm² | 435 mm² |
Paquete | — | FC-LGA10 |
Fabricante | — | Intel |
Frecuencia | 2.6 GHz | 1800 MHz |
---|---|---|
Frecuencia turbo | up to 3.3 GHz | up to 2.3 GHz |
Frecuencia de reloj base | 200 MHz | 100 MHz |
Multiplicador | 13.0x | 18.0x |
Multiplicador desbloqueado | No | No |
TDP | 140 W | 70 W |
Voltaje | — | 1.35 V |
Mercado | Server/Workstation | Server/Workstation |
---|---|---|
Estado de producción | End-of-life | unknown |
Fecha de publicación | Nov 14th, 2011 | Mar 6th, 2012 |
Nombre Clave | Interlagos | Sandy Bridge-EP |
Generación | Opteron | Xeon E5 |
Parte | OS6282YETGGGU | SR0H0SR0KL |
Soporte de memoria | DDR3 | DDR3 Quad-channel |
Memoria ECC | No | Yes |
PCI Express | Gen 2 | Gen 3 |
Número de núcleos | 16 | 8 |
---|---|---|
Número de hilos | 16 | 16 |
SMP # CPUs | 4 | 2 |
Gráficos integrados | — | — |
Caché L1 | 768K | 64K (per core) |
---|---|---|
Caché L2 | 16MB | 256K (per core) |
Caché L3 | 8MB (per die) | 20MB (shared) |
Notas | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). 8MB L3 cache shared per eight cores (per die). 14MB total L3 cache available when using HT Assist. | SR0H0: C1 Stepping SR0KL: C2 Stepping |
---|
8.0GT/s QPI | — | Yes |
---|---|---|
AES | Yes | — |
AES-NI | — | Yes |
AMD-V | Yes | — |
AMD64 | Yes | — |
AVX | Yes | Yes |
CLMUL | Yes | — |
CVT16 | Yes | — |
EIST | — | Yes |
EVP | Yes | — |
FMA4 | Yes | — |
HTT | — | Yes |
Intel 64 | — | Yes |
MMX | Yes | Yes |
SSE | Yes | Yes |
SSE2 | Yes | Yes |
SSE3 | Yes | Yes |
SSE4.1 | Yes | — |
SSE4.2 | Yes | Yes |
SSE4A | Yes | — |
SSSE3 | Yes | Yes |
TXT | — | Yes |
VT-d | — | Yes |
VT-x | — | Yes |
XD bit | — | Yes |
XOP | Yes | — |