Socket | AMD Socket C32 | Intel Socket 1200 |
---|---|---|
Tamaño del proceso | 32 nm | 14 nm |
Transistores | 1,200 million | unknown |
Tamaño de Die | 315 mm² | unknown |
Paquete | — | FC-LGA1200 |
Fabricante | — | Intel |
tCaseMax | — | 72°C |
tJMax | — | 100°C |
Frecuencia | 3.1 GHz | 3.8 GHz |
---|---|---|
Frecuencia turbo | up to 3.8 GHz | up to 4.5 GHz |
Frecuencia de reloj base | 200 MHz | 100 MHz |
Multiplicador | 15.5x | 38.0x |
Multiplicador desbloqueado | No | No |
TDP | 95 W | 65 W |
Mercado | Server/Workstation | Desktop |
---|---|---|
Estado de producción | unknown | Active |
Fecha de publicación | Dec 4th, 2012 | Mar 16th, 2021 |
Nombre Clave | Seoul | Comet Lake-R |
Generación | Opteron | Core i3 |
Parte | OS4386WLU8KHK | unknown |
Soporte de memoria | DDR3 | DDR4-2666 MHz Dual-channel |
Memoria ECC | No | No |
PCI Express | — | Gen 3, 16 Lanes(CPU only) |
Número de núcleos | 8 | 4 |
---|---|---|
Número de hilos | 8 | 8 |
SMP # CPUs | 2 | 1 |
Gráficos integrados | — | UHD Graphics 630 |
Caché L1 | 384K | 64K (per core) |
---|---|---|
Caché L2 | 8MB | 256K (per core) |
Caché L3 | 8MB (shared) | 8MB (shared) |
Notas | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). | — |
---|
ABM | — | Yes |
---|---|---|
ADX | — | Yes |
AES | Yes | — |
AES-NI | — | Yes |
AMD-V | Yes | — |
AMD64 | Yes | — |
AVX | Yes | Yes |
AVX2 | — | Yes |
BMI1 | — | Yes |
BMI2 | — | Yes |
CLMUL | Yes | Yes |
CVT16 | Yes | — |
EIST | — | Yes |
EVP | Yes | — |
F16C | — | Yes |
FMA3 | Yes | Yes |
FMA4 | Yes | — |
Intel 64 | — | Yes |
MMX | Yes | Yes |
RdRand | — | Yes |
SSE | Yes | Yes |
SSE2 | Yes | Yes |
SSE3 | Yes | Yes |
SSE4.1 | Yes | — |
SSE4.2 | Yes | Yes |
SSE4A | Yes | — |
SSSE3 | Yes | Yes |
TBT 2.0 | — | Yes |
TSX | — | Yes |
TXT | — | Yes |
VT-d | — | Yes |
VT-x | — | Yes |
XD bit | — | Yes |
XOP | Yes | — |