Socket | AMD Socket G34 | AMD Socket G34 |
---|---|---|
Process size | 32 nm | 32 nm |
Transistors | 2,400 million | 2,400 million |
Die size | 316 mm² | 316 mm² |
Package | — | — |
Frequency | 2.3 GHz | 2.6 GHz |
---|---|---|
Turbo clock | up to 3.2 GHz | up to 3.3 GHz |
Base clock | 200 MHz | 200 MHz |
Multiplier | 11.5x | 13.0x |
Multiplier unlocked | No | No |
TDP | 115 W | 140 W |
Vertical Segment | Server/Workstation | Server/Workstation |
---|---|---|
Production status | End-of-life | End-of-life |
Release date | Nov 14th, 2011 | Nov 14th, 2011 |
Codename | Interlagos | Interlagos |
Generation | Opteron | Opteron |
Part | OS6276WKTGGGU | OS6282YETGGGU |
Memory support | DDR3 | DDR3 |
ECC memory | No | No |
PCI Express | Gen 2 | Gen 2 |
Total Cores | 16 | 16 |
---|---|---|
Total Threads | 16 | 16 |
SMP # CPUs | 4 | 4 |
Integrated graphics | — | — |
Cache L1 | 768K | 768K |
---|---|---|
Cache L2 | 16MB | 16MB |
Cache L3 | 8MB (per die) | 8MB (per die) |
Notes | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). 8MB L3 cache shared per eight cores (per die). 14MB total L3 cache available when using HT Assist. | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). 8MB L3 cache shared per eight cores (per die). 14MB total L3 cache available when using HT Assist. |
---|
AES | Yes | Yes |
---|---|---|
AMD-V | Yes | Yes |
AMD64 | Yes | Yes |
AVX | Yes | Yes |
CLMUL | Yes | Yes |
CVT16 | Yes | Yes |
EVP | Yes | Yes |
FMA4 | Yes | Yes |
MMX | Yes | Yes |
SSE | Yes | Yes |
SSE2 | Yes | Yes |
SSE3 | Yes | Yes |
SSE4.1 | Yes | Yes |
SSE4.2 | Yes | Yes |
SSE4A | Yes | Yes |
SSSE3 | Yes | Yes |
XOP | Yes | Yes |