AMD FX-6200 vs Intel Core i3-6100
Physical Specifications
Socket | AMD Socket AM3+ | Intel Socket 1151 |
---|---|---|
Process size | 32 nm | 14 nm |
Transistors | 1,200 million | 1,400 million |
Die size | 315 mm² | 150 mm² |
Package | µPGA | — |
Foundry | — | Intel |
tCaseMax | — | 65°C |
Performance
Frequency | 3.8 GHz | 3.7 GHz |
---|---|---|
Turbo clock | up to 4.1 GHz | — |
Base clock | 200 MHz | 100 MHz |
Multiplier | 19.0x | 37.0x |
Multiplier unlocked | Yes | No |
Voltage | 1.4 V | — |
TDP | 125 W | 51 W |
Architecture Details
Vertical Segment | Desktop | Desktop |
---|---|---|
Production status | unknown | Active |
Release date | Feb 27th, 2012 | Sep 1st, 2015 |
Codename | Zambezi | Skylake |
Generation | FX | Core i3 |
Part | FD6200FRW6KGU | SR2HG |
Memory support | DDR3 Dual-channel | DDR4-2133 MHz Dual-channel |
ECC memory | No | No |
PCI Express | Gen 2 | Gen 3, 16 Lanes(CPU only) |
Cores
Total Cores | 6 | 2 |
---|---|---|
Total Threads | 6 | 4 |
SMP # CPUs | 1 | 1 |
Integrated graphics | — | Intel HD 530 |
Cache
Cache L1 | 288K | 64K (per core) |
---|---|---|
Cache L2 | 6MB | 256K (per core) |
Cache L3 | 8MB (shared) | 4MB (shared) |
Notes
Notes | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). This processor comes with an unlocked multiplier, allowing users to set the multiplier value higher than the shipped | — |
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Features & Technologies
AES | Yes | — |
---|---|---|
AES-NI | — | Yes |
AMD-V | Yes | — |
AMD64 | Yes | — |
AVX | Yes | Yes |
AVX2 | — | Yes |
CLMUL | Yes | Yes |
CVT16 | Yes | — |
EIST | — | Yes |
EVP | Yes | — |
FMA3 | — | Yes |
FMA4 | Yes | — |
HT3.1 | Yes | — |
HTT | — | Yes |
Intel 64 | — | Yes |
MMX | Yes | Yes |
SSE | Yes | Yes |
SSE2 | Yes | Yes |
SSE3 | Yes | Yes |
SSE4.1 | Yes | Yes |
SSE4.2 | Yes | Yes |
SSE4A | Yes | — |
SSSE3 | Yes | Yes |
TSX | — | Yes |
Turbo Core | Yes | — |
VT-x | — | Yes |
XD bit | — | Yes |
XOP | Yes | — |