AMD A8-4500M vs Intel Pentium G2100T
Physical Specifications
Socket | AMD Socket FS1r2 | Intel Socket 1155 |
---|---|---|
Process size | 32 nm | 22 nm |
Transistors | 1,178 million | unknown |
Die size | 246 mm² | 94 mm² |
Package | µPGA | FC-LGA12C |
Foundry | — | Intel |
tCaseMax | — | 65°C |
Performance
Frequency | 1900 MHz | 2.6 GHz |
---|---|---|
Turbo clock | up to 2.8 GHz | — |
Base clock | 100 MHz | 100 MHz |
Multiplier | 19.0x | 26.0x |
Multiplier unlocked | No | No |
Voltage | 1.3 V | — |
TDP | 35 W | 35 W |
Architecture Details
Vertical Segment | Mobile | Desktop |
---|---|---|
Production status | unknown | unknown |
Release date | May 15th, 2012 | Sep 3rd, 2012 |
Codename | Trinity | Ivy Bridge |
Generation | A8 | Pentium |
Part | AM4500DEC44HJ | SR0UJ |
Memory support | unknown | DDR3 Dual-channel |
ECC memory | No | No |
PCI Express | — | Gen 3, 16 Lanes(CPU only) |
Cores
Total Cores | 4 | 2 |
---|---|---|
Total Threads | 4 | 2 |
SMP # CPUs | 1 | 1 |
Integrated graphics | Radeon HD 7640G | Intel HD |
Cache
Cache L1 | 192K | 64K (per core) |
---|---|---|
Cache L2 | 4MB (shared) | 256K (per core) |
Cache L3 | — | 3MB (shared) |
Notes
Notes | 16KB L1 data cache per core. 64KB L1 instruction cache shared per two cores (per module). 2MB L2 cache shared per two cores (per module). 497MHz integrated graphics base core frequency, 655MHz maximum dynamic core frequency | Intel HD frequency: 650-1050MHz |
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Features & Technologies
AES | Yes | — |
---|---|---|
AMD-V | Yes | — |
AMD64 | Yes | — |
AVX | Yes | — |
CLMUL | Yes | — |
CVT16 | Yes | — |
EIST | — | Yes |
EVP | Yes | — |
F16C | Yes | — |
FMA3 | Yes | — |
FMA4 | Yes | — |
Intel 64 | — | Yes |
MMX | Yes | Yes |
SSE | Yes | Yes |
SSE2 | Yes | Yes |
SSE3 | Yes | Yes |
SSE4.1 | Yes | Yes |
SSE4.2 | Yes | Yes |
SSE4A | Yes | — |
SSSE3 | Yes | Yes |
Smart Cache | — | Yes |
Turbo Core | Yes | — |
VT-x | — | Yes |
XD bit | — | Yes |
XOP | Yes | — |